1. Technical Field
The present invention relates to a thin film transistor used for electro-optic devices, for example, a liquid crystal device and the like, and to an electro-optic device and an electronic apparatus.
2. Related Art
Thin film transistors have been used as switching elements for pixels or drive circuits in electro-optic devices such as a liquid crystal device and the like, for example, an active matrix-type liquid crystal display. For example, transistors for pixels are adapted for on-off control of image signals supplied to pixel electrodes. A transistor known as such a thin film transistor includes a gate electrode formed on a semiconductor layer through an insulating film, a channel region disposed in the semiconductor layer immediately below the gate electrode, and source and drain regions disposed in the semiconductor layer on both sides of the channel region.
Since it is necessary for such a thin film transistor to hold an image signal during the time from the supply of an image signal to a pixel electrode to the supply of a next image signal (i.e., within one frame), the OFF-current (Ioff), i.e., leakage current, is required to be small. In addition, a sufficient ON-current (Ion) is required for supplying an image signal to the pixel electrode. In particular, an image signal is required to be supplied within a shorter time with a recent increase in number of pixels, i.e., increase in definition.
Therefore, in order to comply with the above requirements, a so-called LDD (Light Doped Drain) structure thin film transistor has been proposed as a structure for decreasing a leakage current, in which a low-concentration impurity region having a lower impurity concentration than that in a channel region and source and drain regions is interposed between the channel region and the source and drain regions disposed on both sides of the channel region (refer to, for example, Japanese Unexamined Patent Application Publication No. 2002-190597).
FIG. 11 shows an example of the above-described LDD-structure thin film transistor, in which FIG. 11A is a plan view, FIG. 1B is a sectional view taken along line XIB-XIB in FIG. 11A in the channel length direction, and FIG. 11C is a sectional view taken along line XIC-XIC in FIG. 11A in the channel width direction. A thin film transistor 1 shown in the drawings includes a semiconductor layer 3 composed of polysilicon or the like and formed on a substrate (not shown) composited of quartz, glass, silicon, or the like, and a gate electrode 5 composed of low-resistance polysilicon or the like and formed on the semiconductor layer 3 through an insulating layer 4 composed of silicon oxide or the like. In addition, a channel region 30 is provided in the semiconductor layer 3 immediately below the gate electrode 5, and source and drain regions 33 and 34 are provided in the semiconductor layer 3 on both sides of the channel region 30 through respective LDD regions 32.
Each of the regions 30 to 34 is formed by ion implantation for introducing (doping) predetermined conductive impurities into the semiconductor layer 3. For example, in an N-channel-type transistor, generally, the N type is considered as first conductivity type, and the opposite conductivity type (different type) impurities, i.e., P-type impurities, are introduced into the channel region 30. Further, low-concentration N-type impurities are introduced into the LDD regions 32, and high-concentration N-type impurities are introduced into each of the source and drain regions 33 and 34. In a P-channel-type transistor, the conductivity types of impurities introduced are opposite to the above. In any one of the cases, N-type and P-type impurities may be introduced into the channel region 30, and no impurity may be introduced into the channel region 30.
However, a thin film transistor having the above-described configuration has the problem that it is difficult to secure a sufficiently high ON-current and sufficiently decrease a leakage current. The reason for this is the following: The ON-current of the thin film transistor is determined by the sheet resistance of the source and drain regions and the bulk resistivity of the semiconductor layer composed of polysilicon or the like. In addition, leakage of the source and drain regions is related to the amount of crystal defects in a PN junction (the energy of ion implantation and the amount of ions implanted, the degree of repair and recovery of lattice defects, and the like at the time of ion implantation) and the electric field strength (the impurity concentration in the semiconductor layer, the channel region, and the source and drain regions). Therefore, in order to decrease the impurity concentration at the PN junction, it is necessary to decrease the amount of channel doping (CD) in the LDD regions (N-regions) provided between the channel region and the source and drain regions. However, under the present situation, the amount is about 10 to 70%, and the dose in the source and drain regions is excessive (about 2 times or more the requirement). Under the present conditions, impurities are introduced over the entire surface of a channel doping region. Therefore, the sheet resistance is high for the high impurity concentration, and thus the ON-current is decreased and defects occur in the LDD regions at the time of impurity implantation, thereby causing the problem of increasing the leakage current.
The thin film transistor has a structure in which boundaries are formed at the ends of the semiconductor layer by usual etching, and the ends are covered with the gate electrode. The ends of the semiconductor layer covered with the gate electrode (in FIG. 11A, near regions surrounded by one-dot chain lines) are regions including etching damage, and thus the function of channel doping is different from in other regions of the semiconductor layer. Therefore, the threshold voltage in the end surfaces becomes smaller than that in the other regions of the semiconductor layer, thereby forming two types of transistors. As a result, as shown in FIG. 12, in the transmission characteristics of a transistor, there occurs the problem referred to as “kink” or “hump” (hereinafter generally named “hump” in this specification) that the ON-current decreases as shown by a one-dot chain line in FIG. 12.